JP's Techblog

Quickly Estimating the Size of Digital Designs

Experienced developers have some intuition how a hardware description maps to circuits, enabling them to optimize code for circuit area or speed instinctively. But like most of the time, checking is better than (educated) guessing. ...

Getting Started with OSS EDA for ASIC Development

Open source EDA tools and open source PDKs for various technologies have recently matured a lot. Here’s a simple and quick way to set up the development environment for those and get started with development. ...

Debugging NEORV32 Applications on the Tang Nano

The Tang Nano 20K board programs the Gowin FPGA using the JTAG protocol. Reusing that JTAG connection for our applications means we don’t need an external JTAG probe for software debugging using NEORV32’s On-Chip-Debugger. ...

Dual-Purpose Pins with Gowin FPGAs and OSS Tools

The Gowin series of FPGA support configuration pin reuse on some special dual-purpose pins. Those pins are used during programming of the FPGA, e.g. for JTAG or as READY and DONE signals. When enabling pin reuse, they can be used as normal GPIO pins by the FPGA bitstream after configuration. The OSS toolchain supports setting these flags and here’s how. ...

SPI Flash Write Protect Signals and NEORV32

NEORV32 does not have any dedicated output pin for the SPI flash write protect signal. On boards like the Tang Nano 20K, not driving this pin however means we can’t write to SPI flash. This breaks the upload firmware function in the bootloader, so here’s how to fix this. ...

Using Cocotb to Test Custom Wishbone Slaves

Cocotb is a convenient way to write your hardware verification tests in Python. Let’s see how to use it with the OSS toolchain. ...

Recompilling the NEORV32 Bootloader

The NEORV32 default bootloader has various configuration options. Here’s how to modify and recompile it. ...

Dev Containers Tricks for Distrobox

Dev Containers is a convenient way to develop in VS Code, whereas distrobox enables convenient GUI and device access in containers. Both concepts can be combined using VS Code’s Attach to running container command, but there are some things to remember. ...

The NEORV32 RISC-V SoC on Tang Nano FPGAs

NEORV32 is an Open Source RISC-V SoC written in VHDL. The CPU neither the smallest nor the fastest RISC-V core, but its main benefit is the complete ecosystem: Not only does it provide peripherals such as I2C, SPI, GPIO and more. It also ships ready-to-use drivers and extensive developer and user documentation. And if bare-metal is not enough, it also offers a FreeRTOS port. Let’s see how we can port NEORV32 to the Tang Nano FPGA. ...

OSS VHDL and Verilog Development on Tang Nano FPGAs

There’s some good documentation on how to get started with OSS development for the Tang Nano FPGA series, but there’s no complete tutorial for VHDL and manual compilation. This post will explain how to set up tools, use Verilog or VHDL and how to mix them, how to compile everything manually and how to program the FPGA. In addition, I’ll show how to use the PLL and how to get a blinky demo running. ...