NEORV32 is an Open Source RISC-V SoC written in VHDL. The CPU neither the smallest nor the fastest RISC-V core, but its main benefit is the complete ecosystem: Not only does it provide peripherals such as I2C, SPI, GPIO and more. It also ships ready-to-use drivers and extensive developer and user documentation. And if bare-metal is not enough, it also offers a FreeRTOS port. Let’s see how we can port NEORV32 to the Tang Nano FPGA. ...
There’s some good documentation on how to get started with OSS development for the Tang Nano FPGA series, but there’s no complete tutorial for VHDL and manual compilation. This post will explain how to set up tools, use Verilog or VHDL and how to mix them, how to compile everything manually and how to program the FPGA. In addition, I’ll show how to use the PLL and how to get a blinky demo running. ...
The Upduino FPGA development board is a cheap way to start with (OSS) FPGA development on the Lattice ICE40 platform. Unfortunately, there are few peripherals on the PCB and there’s no official way for communicate between FPGA application and PC. This post explains how we can reuse the FPGA programmer to transmit data to the FPGA without any additional hardware, using only the programmer USB port. ...