The NEORV32 RISC-V SoC on Tang Nano FPGAs

NEORV32 is an Open Source RISC-V SoC written in VHDL. The CPU neither the smallest nor the fastest RISC-V core, but its main benefit is the complete ecosystem: Not only does it provide peripherals such as I2C, SPI, GPIO and more. It also ships ready-to-use drivers and extensive developer and user documentation. And if bare-metal is not enough, it also offers a FreeRTOS port. Let’s see how we can port NEORV32 to the Tang Nano FPGA. ...

February 27, 2025 · 8 min · Johannes Pfau

OSS VHDL and Verilog Development on Tang Nano FPGAs

There’s some good documentation on how to get started with OSS development for the Tang Nano FPGA series, but there’s no complete tutorial for VHDL and manual compilation. This post will explain how to set up tools, use Verilog or VHDL and how to mix them, how to compile everything manually and how to program the FPGA. In addition, I’ll show how to use the PLL and how to get a blinky demo running. ...

February 26, 2025 · 12 min · Johannes Pfau

Using MPSSE Mode with libftdi

FTDI chips are commonly used for FPGA boards and microcontroller programmer boards. Apart from basic UART, advanced FTDI chips also support synchronous IO using the MPSSE mode. Unfortunately, examples for MPSSE are outdated, Windows-only or otherwise limited. This tutorial therefore explains the MPSSE basics and presents a simple SPI communication example for an FT232H controller using libftdi. ...

February 15, 2025 · 7 min · Johannes Pfau