OSS EDA

Quickly Estimating the Size of Digital Designs

Experienced developers have some intuition how a hardware description maps to circuits, enabling them to optimize code for circuit area or speed instinctively. But like most of the time, checking is better than (educated) guessing. ...

Getting Started with OSS EDA for ASIC Development

Open source EDA tools and open source PDKs for various technologies have recently matured a lot. Here’s a simple and quick way to set up the development environment for those and get started with development. ...

The NEORV32 RISC-V SoC on Tang Nano FPGAs

NEORV32 is an Open Source RISC-V SoC written in VHDL. The CPU neither the smallest nor the fastest RISC-V core, but its main benefit is the complete ecosystem: Not only does it provide peripherals such as I2C, SPI, GPIO and more. It also ships ready-to-use drivers and extensive developer and user documentation. And if bare-metal is not enough, it also offers a FreeRTOS port. Let’s see how we can port NEORV32 to the Tang Nano FPGA. ...

OSS VHDL and Verilog Development on Tang Nano FPGAs

There’s some good documentation on how to get started with OSS development for the Tang Nano FPGA series, but there’s no complete tutorial for VHDL and manual compilation. This post will explain how to set up tools, use Verilog or VHDL and how to mix them, how to compile everything manually and how to program the FPGA. In addition, I’ll show how to use the PLL and how to get a blinky demo running. ...

Reusing the Upduino Programmer for USB→FPGA Communication

The Upduino FPGA development board is a cheap way to start with (OSS) FPGA development on the Lattice ICE40 platform. Unfortunately, there are few peripherals on the PCB and there’s no official way for communicate between FPGA application and PC. This post explains how we can reuse the FPGA programmer to transmit data to the FPGA without any additional hardware, using only the programmer USB port. ...

Running the TinyTapeout Flow Locally

Tiny Tapeout has a local hardening guide to build your design locally. However, the guide does not list required system dependencies and is a bit difficult to follow. This guide aims to be more complete. ...

Verilator for Verilog Testbenches

Verilator has traditionally been used for co-simulation, with testbenches written in C++. With recent versions, it can now also handle pure Verilog simulation. Here’s how. ...